1. Field of the Invention
The present invention relates to a method for manufacturing a CMOS image sensor. More specifically, the present invention relates to a method for manufacturing a CMOS image sensor, capable of preventing dopants implanted with high energy from penetrating into a lower part of a gate electrode when a photodiode is formed, thereby preventing current leakage of a transistor and variation of a threshold voltage.
2. Description of the Related Art
In general, an image sensor is a semiconductor device for converting optical images into electric signals, and is classified into a charge coupled device (CCD) and a CMOS image sensor.
The CCD has a plurality of photodiodes (PDs), which are arranged in the form of a matrix in order to convert optical signals into electric signals. The CCD includes a plurality of vertical charge coupled devices (VCCDs) provided between photodiodes vertically arranged in the matrix so as to transmit electrical charges in the vertical direction when the electrical charges are generated from each photodiode, a plurality of horizontal charge coupled devices (HCCDs) for transmitting the electrical charges that have been transmitted from the VCCDs in the horizontal direction, and a sense amplifier for outputting electric signals by sensing the electrical charges being transmitted in the horizontal direction.
However, such a CCD has various disadvantages, such as a complicated drive mode, high power consumption, and so forth. Also, the CDD requires multi-step photo processes, so the manufacturing process for the CCD is complicated. In addition, since it is difficult to integrate a controller, a signal processor, and an analog/digital converter (A/D converter) onto a single chip of the CCD, the CCD is not suitable for compact-size products.
Recently, the CMOS image sensor is spotlighted as a next-generation image sensor capable of solving the problem of the CCD. The CMOS image sensor is a device employing a switching mode to sequentially detect an output of each unit pixel by means of MOS transistors, in which the MOS transistors are formed on a semiconductor substrate corresponding to the unit pixels through a CMOS technology using peripheral devices, such as a controller and a signal processor. That is, the CMOS sensor includes a photodiode and a MOS transistor in each unit pixel, and sequentially detects the electric signals of each unit pixel in a switching mode to realize images.
Since the CMOS image sensor makes use of the CMOS technology, the CMOS image sensor has advantages such as the low power consumption and simple manufacturing process with a relatively smaller number of photo processing steps. In addition, the CMOS image sensor allows the product to have a compact size, because the controller, the signal processor, and the A/D converter can be integrated onto a single chip of the CMOS image sensor. Therefore, CMOS image sensors have been extensively used in various applications, such as digital still cameras, digital video cameras, and so forth.
Hereinafter, a method for manufacturing a conventional CMOS image sensor will be described.
FIGS. 1A to 1C are sectional views showing the conventional CMOS image sensor.
As shown in FIG. 1A, a low-density P type (P-) epitaxial layer 110 is formed on a P type semiconductor substrate 100. Then, an exposure and development process is performed with respect to the resultant structure by using a mask defining an active area and an isolation area, and the epitaxial layer 110 formed in the isolation area is etched to a predetermined depth, thereby forming a trench. An O3 TEOS film is formed on the semiconductor substrate 100 such that the O3 TEOS film is filled in the trench, and then is patterned through a chemical mechanical polishing (CMP) process such that the O3 TEOS film remains only in the trench, thereby forming an isolation layer 120 in the isolation area.
Then, an insulating layer and a conductive layer are sequentially formed on the entire surface of the semiconductor substrate 100, and then selectively removed, thereby forming a gate electrode 140 and a gate insulating layer 130.
Subsequently, a photoresist pattern (not shown) is formed such that only a portion of the epitaxial layer 110 corresponding to a source/drain area is exposed, and low-density N type dopants are implanted into the resultant structure, thereby forming a low-density N type impurity area for lightly doped drain (LDD).
As shown in FIG. 1B, a photoresist film (not shown) is deposited on the entire surface of the semiconductor substrate, and then an exposure and development process is performed with respect to the resultant structure, thereby forming a photoresist pattern such that a photodiode area is exposed. At this time, the photoresist pattern allows a portion of the gate electrode 140 to be exposed. Then, N type dopants are implanted into the epitaxial layer 110 formed in the photodiode area through a high-energy ion implantation process, and a diffusion process is performed, thereby forming an N type impurity diffusion area 160. Thereafter, the photoresist pattern is removed.
As shown in FIG. 1C, an insulating layer is deposited on the entire surface of the semiconductor substrate, and an etch back process is performed with respect to the resultant structure, thereby forming spacers 170 at both sides of the gate electrode 140. Subsequently, a photoresist pattern (not shown) is formed such that the spacer formed in a source/drain area or in the vicinity of the source/drain area can be exposed, and then high-density N type dopants are implanted into an upper part of the source/drain area, thereby forming a high-density N type impurity area 180. In addition, a photoresist pattern (not shown) is formed such that the spacer formed in the photodiode area or in the vicinity of the photodiode area can be exposed, and then P type dopants are implanted into an upper part of the N type impurity diffusion area 160, thereby forming a photodiode P type impurity diffusion area 190.
However, during the high-energy N type dopant implantation process for forming a photodiode, N type dopants may be doped to a channel area at a lower part of the gate insulating layer 130 through the gate electrode 140 due to high-energy ion implantation.
In other words, since the N type dopants are doped to the extent of the channel area formed below the gate electrode 140, a threshold value Vth of a transistor is reduced to a level equal to or less than a target value, so an off leakage current may increase.